Today's electronic devices contain sophisticated circuits, many of which have been made possible by fabricating highly dense arrays of conductors and components. These conductors and components are typically fabricated by using photolithographic techniques. As the demand for more complex circuits (and higher capacity in memory devices made from these complex circuits) increases, however, the need to form even finer features rises. In the case of memory devices, higher-capacity storage requires finer conductors and spacing.
The limits to photolithographic techniques are related to the desired feature size and the wavelength of the light used to project an image on the semiconductor substrate. This projection is performed using reticules that can be very costly to produce. For this reason, it is desirable to limit the number of reticules required. As the extreme limits of the photolithographic process are approached, however, the spreading of the edges of the projected images can cause artifacts where these edges overlap and form undesired projected images due to the additive nature of the process. One way to avoid this effect is to maintain a greater spacing between desired features so as to avoid the edge overlapping. This greater spacing prevents the tight packing of lines desired for high density memory arrays, however.
A technique to retain the tight packing of lines while avoiding this additive edge effect is double-patterning, a technique in which one mask is used to project the image of only a subset of desired features (e.g., even-numbered array lines), thereby leaving wider spacing between those even lines so as to avoid the additive edge effect. A second mask is then used to project the remaining features (e.g., odd-numbered array lines, centered in the spaces between the even-numbered lines) and thus create the desired high density packing. The downside to this technique is the increase in the number of required masks.
In the case of diode-array memories in particular, the need for smaller diode formation to fit within the pattern of finer conductors and spacing introduces additional problems. For example, the vertically formed diode at each memory cell location is sometimes created by overlapping a row and column line thereby forming a square (or nearly square) feature which is the footprint of the vertical diode. However, in those methods in which the square feature is a hole in which a diode is grown, the corners can cause the formation of stacking faults while silicon is epitaxially grown in the holes. Also, these corners can be a source of current leakage in the formed diodes during operation. In addition, the information-storage element formed using the diode of a diode-array memory must have a consistent dimension across all instances of the element across die in order to prevent variations in the operating parameters that would render both the programming voltages and currents as well as the read threshold between a one bit and a zero bit difficult to calibrate. A need therefore exists for a way to create high-density arrays of elements using a minimum number of masks.